The invention pertains to semiconductor fabrication. More particularly, the invention pertains to patterning of small features in integrated circuits.
As the designs of semiconductor circuitry become smaller, problems with the limitations and tolerances of the optical systems used in photolithography become more prevalent, especially with regards to the etching of small features.
For example, the problem of line end shortening (LES) is primarily the result of the limitations of the optics used in photolithography. Particularly, LES generally refers to the problem wherein a line of photoresist to be formed on a substrate ends up being shorter than what was intended by the design, e.g., shorter than the corresponding line on the mask. This is due largely to the fact that the amount of photoresist that is exposed through the mask to light generally will not exactly match that dictated by the mask due to diffraction of light around the edges between the opaque regions and the transparent regions of the mask and due to complex interactions between nearby features (commonly known as proximity effects). Aspects of line end shortening include corner rounding, wherein corners of the line become rounded, and overall line end shortening.
The issue of line end shortening is particularly relevant to the fabrication of gates in SRAM (Static Random Access Memory) transistors. Specifically, the material (typically polysilicon) deposited on a semiconductor to form the gate electrode of a transistor in a SRAM is generally called a line. With reference to exemplary FIG. 1, which shows a small portion of a SRAM integrated circuit, typically, a plurality of lines 112a, 112b, 112c of different transistors are straight, coaxial with each other, and are separated from each other by small gaps 114a, 114b. Furthermore, the lines 112 usually are perpendicularly intersected by other lines 116 (which, in this case, refer to shallow trench level isolation). The common area between 116 and 112 define the active area of a transistor. As SRAM transistors become smaller and more densely packed, the line tip to tip distances, i.e., the gaps 114, between the coaxial lines 112, become smaller.
For any given transistor design, there is a minimum amount of overhang 118 that must be maintained in order to prevent leakage between the gate, source and drain of the transistor. Also, there must be a minimum gap 114 between the ends of the lines 112 between adjacent transistors in order to prevent leakage between the adjacent transistors.
Accordingly, line end shortening is a particular problem with respect to the fabrication of SRAMs because it often is important to maintain a minimum overhang 118 and a minimum line end to line end spacing (hereinafter tip to tip gap) 114, while simultaneously making the tip to tip gap as small as possible in order to pack the transistors as tightly together as possible.
Several solutions have been proposed to address the line end shortening problem. In one such solution, the mask is designed with longer lines than desired based on the assumption that line end shortening will occur. However, as the tip to tip gap becomes smaller, this solution becomes less than optimal. Particularly, the lines on the mask can only be lengthened to a limited extent because the adjacent coaxial mask lines cannot meet as there would no longer be a gap between the line ends in the mask.
Furthermore, the amount of line end shortening and corner rounding that can occur can only be determined within a certain tolerance, and thus this solution can only be taken so far. Furthermore, the features on the mask themselves (e.g., the lengths of the lines on the mask) can be produced only to certain tolerances. Further, due to the limitations of the optics, any error in the mask can generally be expected to be magnified up to about six fold, and sometimes even more, when transferred to the semiconductor through photolithography.